LAUSR

In the last few decades we have witnessed an increase in CPU performance, which has been made possible thanks to the increase in the clock frequency and the increase in the number of transistors in the unit of space. In the last few years, however, we reached the limit for the clock and for the miniaturization of the transistor grid. Beyond this growth new problems arose such as the disposal of the produced heat and the minimum distance to be respected between elements for the electrical signals transfer. So the chip makers, to further increase the processing power of the processors, started to insert more cores on the same chip. The presence of several cores undoubtedly improves performance and improves consumption, but the ability to transfer data between cores and components remains limited by the number of pins of the cores themselves. Furthermore, it is necessary to manage the synchronization between cores during the access to common resources and all those multi-core architectures typical problems. This article provides a different approach to improve the computing capacity of the CPUs that is based on the extension of the binary system in a multi-value coding system or, commonly, called MVL. Although this direction has already been explored, the idea behind the study is in the representation of the generic function in the MVL domain. This representation has a link to the binary system and a surprisingly greater simplicity of the corresponding digital circuits (combinatorial and sequential). A different mathematical approach is thus provided for the realization of the multivalue logic gates. This could enable the use of different data encoding systems no longer linked to the voltage value of a signal but to other physical quantities as it happens at present, for example, in the world of telecommunications.