This paper presents a digital implementation of modified synchronous reference frame in which the Phase Locked Loop (PLL) is customized to get the angle for the reference frames from the… Click to show full abstract
This paper presents a digital implementation of modified synchronous reference frame in which the Phase Locked Loop (PLL) is customized to get the angle for the reference frames from the supply voltage by Enhanced Phase Locked Loop (EPLL). The extracted harmonics currents are given to an Artificial Neural Network based Space Vector Pulse Width Modulation (ANNSVPWM) which has better switching control and reduced stress on the switches to cancel the distortions at the Point of Common Coupling (PCC). The algorithm was modelled and simulated by Matlab/Simulink to validate the results. The experimental verification is carried on Field Programmable Gate Array (FPGA) Spartan board to check the effectiveness of the control strategy being implemented and the results conclude that the Total Harmonic Distortion (THD) values are below the required levels of power quality standards.
               
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