LAUSR

In space, high-energy particle radiation poses a serious threat to the data stability and reliability of SRAM. Existing radiation-tolerant techniques, such as Triple Modular Redundancy (TMR) and Error Correction Code (ECC), have disadvantages such as large area, high power consumption, and additional delay, making them unsuitable for small satellite systems. To overcome these limitations, this paper proposes a 16-transistor-based radiation-tolerant SRAM cell, WRTU-16T, which applies a read-decoupled structure and a charge-sharing suppression mechanism. The proposed structure effectively isolates the storage node from external disturbances and improves the recovery capability for single-event inversion (SEU) and multiple-node inversion (SEMNU) by reducing charge loss. WRTU-16T shows superior performance in terms of write delay, charge recovery capability (Qc), hold power, and word line write threshold voltage (WWTV) compared to existing radiation-tolerant SRAM designs. The integrated circuit is implemented using a 90 nm CMOS process and has an operating voltage of 1V.