LAUSR

A microelectromechanical systems (MEMS) solid-state logic control chip with three layers—diversion layer, control layer, and substrate layer—is designed to satisfy fuse miniaturization and integration requirements. A mathematical model is established according to the heat conduction equation, and the limit conditions of different structures are presented. The finite element multi-physical field simulation method is used to simulate the size and the action voltage of the diversion layer of the control chip. Based on the surface silicon process, fuse processing, and testing with the MEMS solid-state fuse-logic control chip, a diversion layer constant current, maximum current resistance test, and a control layer of different bridge area sizes, the bridge area size is 200 × 30 μm, and the minimum electrical explosion voltage is 23.6 V. The theoretical calculation results at 20 V and 100 μF demonstrate that the capacitor energy is insufficient to support the complete vaporization of the bridge area, but can be partially vaporized, consistent with the experimental results.