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Designing a hetrostructure junctionless-field effect transistor (HJL-FET) for high-speed applications

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This paper explores the impacts of both the strained silicon layer thickness, D, and germanium mole fraction, X, on the electrical characteristics of a heterostructure junctionless (HJL)-FET by a numerical… Click to show full abstract

This paper explores the impacts of both the strained silicon layer thickness, D, and germanium mole fraction, X, on the electrical characteristics of a heterostructure junctionless (HJL)-FET by a numerical simulator. The gate controllability on the Si1−XGeX layer has been increased by reducing D for a given X, hence, OFF-state current decreases. The permittivity factor increasing prevails to the band gap reducing in the Si0.3Ge0.7 layer, for D = 0.5 nm. As a result, in a 15 nm channel length, the OFF-state current of HJL-FET with D = 0.5 nm and X = 0.7 is improved by 95%, as compared to that of the regular JL-FET. Therefore, D and X parameters can be considered to reduce the OFF-state current of HJL-FET, even without pushing the gate to a large negative voltage. We propose a novel “Modified HJL-FET (MHJL-FET)” structure which improves the subthreshold slope (SS) in comparison with HJL-FET, by employing the doping engineering. The Si1−XGeX layer of MHJL-FET has a lower doping density in comparison with the strained silicon layer. The doping engineering not only reduces SS by 10%, but also increases the ION/IOFF ratio two orders of magnitude, for 10 nm channel length. The benchmarking results indicate that the MHJL-FET device is promising for future logic transistor applications.

Keywords: junctionless; layer; hjl; hjl fet; transistor

Journal Title: Journal of the Korean Physical Society
Year Published: 2017

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