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Published in 2021 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2021.3057575
Abstract: We demonstrate a four-to-one 100-GS/s time interleaver realized in a 55-nm BiCMOS technology. The interleaver comprises two stages of two-to-one sub-interleavers. Each sub-interleaver is implemented using a return-to-zero generation and summing architecture. This sub-interleaver architecture…
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Keywords:
100 four;
interleaver;
analog;
four one ... See more keywords