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Published in 2018 at "IEEE Transactions on Circuits and Systems I: Regular Papers"
DOI: 10.1109/tcsi.2018.2813326
Abstract: Subthreshold and near-threshold operations are viable approaches towards reducing both static and dynamic power in Static Random Access Memory (SRAM). However, supply scaling in SRAM cells is severely limited by process variations. Additionally, cell performance…
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Keywords:
10t sram;
bit;
sub;
tex math ... See more keywords
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3
Published in 2023 at "IEEE Transactions on Circuits and Systems I: Regular Papers"
DOI: 10.1109/tcsi.2023.3241385
Abstract: In this paper, we present a 10T SRAM compute-in memory (CiM) macro to process the multiplication-accumulation (MAC) operations between ternary-inputs and binary-weights. In the proposed 10T SRAM bitcell, the charge-domain analog computations are employed to…
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Keywords:
neural network;
2941 tops;
charge domain;
10t sram ... See more keywords
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Published in 2019 at "IEEE Transactions on Electron Devices"
DOI: 10.1109/ted.2019.2945533
Abstract: We experimentally demonstrate the first static random-access memory (SRAM) arrays based on carbon nanotube (CNT) field-effect transistors (CNFETs). We demonstrate 1 kbit (1024) 6 transistor (6T) SRAM arrays fabricated with complementary metal-oxide-semiconductor (CMOS) CNFETs (totaling…
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Keywords:
sram cells;
carbon nanotube;
10t sram;
kbit ... See more keywords
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1
Published in 2017 at "Journal of Low Power Electronics and Applications"
DOI: 10.3390/jlpea7030024
Abstract: In this paper, an ultra-low power (ULP) 10T static random access memory (SRAM) is presented for Internet of Things (IoT) applications, which operates at sub-threshold voltage. The proposed SRAM has the tendency to operate at…
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Keywords:
10t sram;
ultra low;
power;
sram ... See more keywords