A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations
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DOI: 10.1109/tvlsi.2016.2576468
Abstract: A 10-bit 500-MS/s partial-interleaving pipelined successive approximation register (SAR) analog-to-digital converter (ADC) architecture is presented that implements a full-speed 2-bit/cycle SAR at the front end with interleaved residue MDACs and SAR ADCs at the back… read more here.
Keywords: interleaving pipelined; pipelined sar; partial interleaving; 500 partial ... See more keywords