Articles with "5nm eot" as a keyword



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Demonstration of 2e12cm2eV1 2D-oxide interface trap density on back-gated MoS2 flake devices with 2.5nm EOT

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Published in 2017 at "Microelectronic Engineering"

DOI: 10.1016/j.mee.2017.05.006

Abstract: This study reports on the low interface trap density obtained from MOS capacitors and transistors with 2.5nm EOT using MoS2 flakes in back-gated configuration. Design ideology to measure thin flake structures is explained. CV measurements… read more here.

Keywords: 5nm eot; interface trap; trap density;