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Published in 2017 at "Microelectronic Engineering"
DOI: 10.1016/j.mee.2017.05.006
Abstract: This study reports on the low interface trap density obtained from MOS capacitors and transistors with 2.5nm EOT using MoS2 flakes in back-gated configuration. Design ideology to measure thin flake structures is explained. CV measurements…
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Keywords:
5nm eot;
interface trap;
trap density;