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Published in 2020 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2020.3017950
Abstract: A framework is presented to identify an optimal accelerated test region and accelerated test conditions for the accelerated test of logic circuits for time-dependent dielectric breakdown (TDDB). Both gate-oxide breakdown and middle-of-line (MOL) TDDB are…
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Keywords:
test;
test conditions;
accelerated test;
optimal accelerated ... See more keywords