A 13-bit 0.005-mm2 40-MS/s SAR ADC With kT/C Noise Cancellation
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DOI: 10.1109/jssc.2020.3016656
Abstract: As any analog-to-digital converter (ADC) with a front-end sample-and-hold (S/H) circuit, successive approximation register (SAR) ADC suffers from a fundamental signal-to-noise ratio (SNR) challenge: its sampling kT/C noise. To satisfy the SNR requirement, the input… read more here.
Keywords: input; adc noise; noise cancellation; sar adc ... See more keywords