Optimal dynamic range scaling of ΔΣ ADC using bias current estimation
Sign Up to like & getrecommendations! Published in 2018 at "Analog Integrated Circuits and Signal Processing"
DOI: 10.1007/s10470-017-1102-4
Abstract: In this paper, optimal dynamic range scaling of ΔΣ ADC using bias current estimation method is proposed. Generally, a different dynamic range scaling gives different feedback factor and effective load capacitance to each integrator in… read more here.
Keywords: adc using; optimal dynamic; scaling adc; range scaling ... See more keywords
A 13-mW 64-dB SNDR 280-MS/s Pipelined ADC Using Linearized Integrating Amplifiers
Sign Up to like & getrecommendations! Published in 2018 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2018.2815654
Abstract: A 12-bit pipelined analog-to-digital converter (ADC) using a new integration-based open-loop residue amplifier topology is presented. The amplifier distortion is cancelled with the help of an analog linearization technique based on a tunable input-driven active… read more here.
Keywords: adc using; adc; sndr 280; calibration ... See more keywords
A 72-dB SNDR 130-MS/s 0.8-mW Pipelined-SAR ADC Using a Distributed Averaging Correlated Level Shifting Ring Amplifier
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2022.3196743
Abstract: This article presents a 14-b 130-MS/s two-stage pipelined-SAR analog-to-digital converter (ADC) using a distributed averaging correlated level shifting (DACLS) ring amplifier as its residue amplifier (RA). Compared to the prior CLS and ACLS techniques that… read more here.
Keywords: adc using; level shifting; level; ring amplifier ... See more keywords