High-performance AES-128 algorithm implementation by FPGA-based SoC for 5G communications
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DOI: 10.11591/ijece.v11i5.pp4221-4232
Abstract: In this research work, a fast and lightweight AES-128 cypher based on the Xilinx ZCU102 FPGA board is presented, suitable for 5G communications. In particular, both encryption and decryption algorithms have been developed using a… read more here.
Keywords: encryption decryption; aes 128; decryption; performance aes ... See more keywords