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Published in 2018 at "IEEE Transactions on Circuits and Systems I: Regular Papers"
DOI: 10.1109/tcsi.2017.2768826
Abstract: The computation-intensive circuit simulation makes the analog circuit sizing challenging for large-scale/complicated analog/RF circuits. A Bayesian optimization approach has been proposed recently for the optimization problems involving the evaluations of black-box functions with high computational…
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Keywords:
bayesian optimization;
optimization;
analog circuits;
optimization approach ... See more keywords
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Published in 2022 at "IEEE Transactions on Circuits and Systems II: Express Briefs"
DOI: 10.1109/tcsii.2022.3199250
Abstract: In this brief we propose a completely novel approach to design robust analog circuits made up only of digital CMOS gates taken from conventional standard-cell libraries. The approach exploits the topology of CMOS NOT, NOR…
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Keywords:
cell;
analog;
standard cell;
inline formula ... See more keywords
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Published in 2019 at "IEEE Transactions on Electron Devices"
DOI: 10.1109/ted.2019.2928484
Abstract: This paper presents functional high-temperature analog circuits in silicon carbide bipolar technology. The circuits will collectively form the analog signal conditioning block for a wireless telemetry system in an extreme environment (above 400°C). The signal…
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Keywords:
analog circuits;
conditioning;
silicon carbide;
carbide bipolar ... See more keywords
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Published in 2022 at "IEEE Transactions on Instrumentation and Measurement"
DOI: 10.1109/tim.2022.3194890
Abstract: In order to reduce the high built-in test (BIT) false alarms of analog circuits caused by intermittent faults, a BIT-based intermittent fault diagnosis method for analog circuits by improved deep forest (DF) classifier is proposed.…
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Keywords:
intermittent faults;
analog circuits;
fault diagnosis;
intermittent fault ... See more keywords