Protecting IP core during architectural synthesis using HLT-based obfuscation
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DOI: 10.1049/el.2017.1329
Abstract: For protecting an intellectual property (IP) core, it must be harder to reverse engineer. Structural obfuscation can play an important role in achieving this goal. A novel structural obfuscation methodology during architectural synthesis using multiple… read more here.
Keywords: using hlt; methodology; architectural synthesis; synthesis using ... See more keywords
Architectural Synthesis of Multi-SIMD Dataflow Accelerators for FPGA
Sign Up to like & getrecommendations! Published in 2018 at "IEEE Transactions on Parallel and Distributed Systems"
DOI: 10.1109/tpds.2017.2746081
Abstract: Field Programmable Gate Array (FPGA) boast abundant resources with which to realise high-performance accelerators for computationally demanding operations. Highly efficient accelerators may be automatically derived from Signal Flow Graph (SFG) models by using architectural synthesis… read more here.
Keywords: architectural synthesis; simd dataflow; multi simd; synthesis multi ... See more keywords