A High Area-Efficiency 14-bit SAR ADC With Hybrid Capacitor DAC for Array Sensors
Sign Up to like & getrecommendations! Published in 2020 at "IEEE Transactions on Circuits and Systems I: Regular Papers"
DOI: 10.1109/tcsi.2020.2998473
Abstract: This paper proposes a high area-efficiency 14-bit column-parallel successive approximation register (SAR) analog-to-digital converter (ADC) for array sensors. A novel hybrid capacitor digital-to-analog converter (CDAC) based on the charge transfer is utilized to increase the… read more here.
Keywords: tex math; capacitor; area; inline formula ... See more keywords
Architectural Comparison Model for Area-Efficient PMAP Turbo-Decoders
Sign Up to like & getrecommendations! Published in 2023 at "IEEE Transactions on Circuits and Systems II: Express Briefs"
DOI: 10.1109/tcsii.2022.3207471
Abstract: In this brief, a methodology to compare high-throughput turbo decoder architectures, is proposed. The model is based on the area-efficiency estimation of different architectures and design choices. Moreover, it is specifically oriented to the exploration… read more here.
Keywords: pmap; area; comparison model; model ... See more keywords
An eDRAM-Based Computing-in-Memory Macro With Full-Valid-Storage and Channel-Wise-Parallelism for Depthwise Neural Network
Sign Up to like & getrecommendations! Published in 2024 at "IEEE Transactions on Circuits and Systems II: Express Briefs"
DOI: 10.1109/tcsii.2024.3375319
Abstract: Computing-in-memory (CIM) provides a highly efficient solution for neural networks in edge artificial intelligence applications. Most SRAM-based CIM designs can achieve high energy efficiency and area efficiency in standard convolutional layer’s multiply-and-accumulate (MAC) operations. However,… read more here.
Keywords: depthwise; efficiency; memory; area efficiency ... See more keywords