Areal Geometric Effects of a ZnO Charge-Trap Layer on Memory Transistor Operations for Embedded-Memory Circuit Applications
Sign Up to like & getrecommendations! Published in 2017 at "IEEE Electron Device Letters"
DOI: 10.1109/led.2017.2729578
Abstract: The areal geometric effects of a ZnO charge-trap layer (CTL) on the device characteristics of a charge-trap memory thin-film transistor were investigated for embedded-memory circuit applications. While the device with a larger overlapped region between… read more here.
Keywords: effects zno; areal geometric; charge trap; geometric effects ... See more keywords