On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming
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DOI: 10.1007/s10710-018-9340-5
Abstract: Evolvable hardware allows the generation of circuits that are adapted to specific problems by using an evolutionary algorithm (EA). Dynamic partial reconfiguration of FPGA LUTs allows making the processing elements (PEs) of these circuits small and compact,… read more here.
Keywords: genetic programming; cartesian genetic; evolvable hardware; array cartesian ... See more keywords