Reliable and high performance asymmetric FinFET SRAM cell using back-gate control
Sign Up to like & getrecommendations! Published in 2020 at "Microelectronics Reliability"
DOI: 10.1016/j.microrel.2019.113545
Abstract: Abstract As the technology scales down, the performance characteristics are degraded and the reliability of digital circuits against soft error and aging effects are reduced. In this paper, we propose a reliable asymmetric FinFET 6T… read more here.
Keywords: asymmetric finfet; sram cell; back gate; finfet sram ... See more keywords
Comparison between nMOS and pMOS Ω-gate nanowire down to 10 nm width as a function of back gate bias
Sign Up to like & getrecommendations! Published in 2019 at "Semiconductor Science and Technology"
DOI: 10.1088/1361-6641/aafccc
Abstract: This paper presents a comparison between nMOS and pMOS Omega-Gate Nanowire for different channel width (W-NW) down to 10 nm as a function of the large back gate bias variation (from +20 to -20 V)… read more here.
Keywords: voltage; back gate; nmos pmos; gate ... See more keywords
Donor implanted back-gates in GaAs for MBE-grown highest mobility two-dimensional electron systems
Sign Up to like & getrecommendations! Published in 2021 at "Semiconductor Science and Technology"
DOI: 10.1088/1361-6641/ac0d9a
Abstract: Three different elements, silicon, selenium, and tellurium, are ion-implanted in gallium arsenide to form a conducting layer that serves as a back-gate to a molecular beam epitaxy overgrown two-dimensional electron gas. While the heavy ion… read more here.
Keywords: silicon selenium; mbe grown; two dimensional; back gate ... See more keywords
Nonlinear behaviors in back-gate effects of FDSOI MOSFETs at cryogenic temperatures
Sign Up to like & getrecommendations! Published in 2024 at "Semiconductor Science and Technology"
DOI: 10.1088/1361-6641/ad5e17
Abstract: In this work, we systematically investigate the DC performance of fully depleted silicon-on-insulator (FD-SOI) MOSFETs at both room and cryogenic temperatures as low as 77 K. The influences of back-gate bias on normal and flip-well… read more here.
Keywords: cryogenic temperatures; back gate; well devices; behaviors back ... See more keywords
Empirical Modeling and Performance Evaluation of Monolithic-3D Dynamic Random-Access Memory
Sign Up to like & getrecommendations! Published in 2025 at "IEEE Access"
DOI: 10.1109/access.2025.3545903
Abstract: Among the various three-dimensional (3D) stacking techniques essential for scaling electronic devices, monolithic-3D (M3D) integration technology offers the highest integration density. However, this technology faces challenges such as sensitivity to high temperatures and electrical interference… read more here.
Keywords: back gate; tex math; interference; inline formula ... See more keywords
Total Ionizing Dose Hardening Methodology in Back Gate Embedded SOI MOSFETs With Ultrathin Buried Oxide
Sign Up to like & getrecommendations! Published in 2025 at "IEEE Electron Device Letters"
DOI: 10.1109/led.2025.3587666
Abstract: A novel total ionizing dose (TID) hardening method is proposed based on the innovative back gate embedded silicon on insulator (BGESOI) technology. By elaborately designing the manufacturing process, the symmetric split gate configuration is constructed… read more here.
Keywords: methodology; back gate; gate embedded; ionizing dose ... See more keywords
Evaluation of Tradeoffs in the Design of FPGA Fabrics Using Electrostrictive 2-D FETs
Sign Up to like & getrecommendations! Published in 2021 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2021.3059979
Abstract: The electrostrictive 2-D field-effect transistor (EFET) is a steep-slope device that promises to offer aggressive length and voltage scalability. Two key features of this device are its high-drive strength with high ON–OFF current ratio and… read more here.
Keywords: tradeoffs design; fpga fabrics; evaluation tradeoffs; design fpga ... See more keywords