A 1.2-GS/s 8-bit Two-Step SAR ADC in 65-nm CMOS With Passive Residue Transfer
Sign Up to like & getrecommendations! Published in 2017 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2017.2682839
Abstract: A high-speed 2b–1b/cycle two-step successive-approximation-register analog-to-digital converter (ADC) exploiting the passive residue transfer technique is reported. The removal of the residue amplifier results in savings in the time and power consumed by the residue transfer… read more here.
Keywords: residue transfer; two step; bit two; passive residue ... See more keywords
A 7-Bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2022.3159569
Abstract: A 7-bit 3 GS/s two-channel time-interleaved two-step flash analog-to-digital converter (ADC) with 7-GHz effective resolution bandwidth (ERBW) is presented. A reference-embedding flash ADC for a fine stage having only a single capacitive digital-to-analog converter improves… read more here.
Keywords: flash adc; two step; step; adc ... See more keywords