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Published in 2019 at "Journal of Materials Chemistry C"
DOI: 10.1039/c8tc06249h
Abstract: High-performance bottom-gate 2D-layered (PEA)2SnI4 field-effect transistors have been fabricated using PVA/CL-PVP as gate dielectric layers.
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Keywords:
bottom gate;
effect transistors;
field effect;
two dimensional ... See more keywords
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Published in 2019 at "IEEE Electron Device Letters"
DOI: 10.1109/led.2019.2931410
Abstract: In this letter, we have fabricated Ge-on-insulator (Ge-OI) junctionless (JL) n-MOSFETs via wafer bonding and epitaxial lift-off (ELO) techniques. We have evaluated the electrical characteristics of Ge-OI JL n-MOSFETs with different thickness of Ge channel…
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Keywords:
bottom gate;
tex math;
inline formula;
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Published in 2018 at "IEEE Transactions on Electron Devices"
DOI: 10.1109/ted.2018.2833057
Abstract: Proper driving of a large-area, high-resolution, and high-frame-rate active-matrix display can be hindered by excessive delay along a signal path, such as a scan line. Depending on the transistor architecture, such delay could be dominated…
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Keywords:
drain regions;
bottom gate;
self aligned;
gate ... See more keywords
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Published in 2018 at "IEEE Transactions on Nanotechnology"
DOI: 10.1109/tnano.2018.2874093
Abstract: A detailed experimental investigation on nanostructured tungsten trioxide (WO3) based bottom gate field effect transistor (FET) is presented. These were fabricated using scalable process and thoroughly characterized for morphology and device performance. It was also…
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Keywords:
bottom gate;
dependent electrical;
sub sub;
temperature dependent ... See more keywords