Performance Bounds of ADC-Based Receivers Due to Clock Jitter
Sign Up to like & getrecommendations! Published in 2023 at "IEEE Transactions on Circuits and Systems II: Express Briefs"
DOI: 10.1109/tcsii.2023.3257844
Abstract: The maximum tolerable clock jitter for high-speed ADCs is pessimistically predicted by Nyquist-rate input sinusoidal tests. We prove that the jitter can be greatly relaxed in the presence of lossy channels in wireline systems. We… read more here.
Keywords: bounds adc; performance bounds; jitter; adc based ... See more keywords