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Published in 2017 at "Electronics Letters"
DOI: 10.1049/el.2017.1029
Abstract: Parallel cyclic redundancy check (CRC) architecture for high-throughput forward error correction decoders in broadband communication systems is proposed. Large amount of data bits are needed to be transmitted in a unit of a transport block…
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Keywords:
parallel crc;
broadband communication;
crc architecture;
architecture ... See more keywords