A saboteur and mutant based built-in self-test and counting threshold-based built-in self repairing mechanism for memories
Sign Up to like & getrecommendations! Published in 2020 at "Journal of Ambient Intelligence and Humanized Computing"
DOI: 10.1007/s12652-020-02284-5
Abstract: In system on chip (SOC) design, memory occupies a large area, if any defects in the memory that will affect the SOC’s total yield. To avoid this, spare rows and columns are added to the… read more here.
Keywords: built self; based built; counting threshold; self test ... See more keywords
A Low-Cost On-Chip Built-In Self-Test Solution for ADC Linearity Test
Sign Up to like & getrecommendations! Published in 2020 at "IEEE Transactions on Instrumentation and Measurement"
DOI: 10.1109/tim.2019.2936716
Abstract: State-of-the-art analog-to-digital converter (ADC) built-in self-test (BIST) methods relax the test stimulus linearity but require a constant voltage shift during testing. A low-cost on-chip BIST solution with a modified R2R digital-to-analog converter (DAC) structure is… read more here.
Keywords: self test; test; low cost; built self ... See more keywords
A Ku-Band Eight-Element Phased-Array Transmitter With Built-in Self-Test Capability in 180-nm CMOS Technology
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2022.3151383
Abstract: In this article, a CMOS Ku -band phased-array transmitter with eight elements is demonstrated. To mitigate the measurement time and complexity, a built-in self-test (BIST) circuit is developed in this chip. A fully symmetrical sampling… read more here.
Keywords: phased array; self test; array transmitter; built self ... See more keywords
Built-In Self-Test of High-Density and Realistic ILV Layouts in Monolithic 3-D ICs
Sign Up to like & getrecommendations! Published in 2023 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2022.3228850
Abstract: Nanoscale interlayer vias (ILVs) in monolithic 3-D (M3D) ICs have enabled high-density vertical integration of logic and memory tiers. However, the sequential assembly of M3D tiers via wafer bonding is prone to variability in the… read more here.
Keywords: self test; realistic ilv; high density; test ... See more keywords
TSV Built-In Self-Repair Architecture for Improving the Yield and Reliability of HBM
Sign Up to like & getrecommendations! Published in 2023 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2023.3248042
Abstract: High-bandwidth memory (HBM) is the latest 3-D-stacked dynamic random access memory (DRAM) standard adopted in Joint Electron Device Engineering Council (JEDEC). It has many advantages, such as high bandwidth, large capacity, and low power consumption,… read more here.
Keywords: tsv built; self repair; yield reliability; built self ... See more keywords
Built-In Self-Test (BIST) Methods for MEMS: A Review
Sign Up to like & getrecommendations! Published in 2020 at "Micromachines"
DOI: 10.3390/mi12010040
Abstract: A novel taxonomy of built-in self-test (BIST) methods is presented for the testing of micro-electro-mechanical systems (MEMS). With MEMS testing representing 50% of the total costs of the end product, BIST solutions that are cost-effective,… read more here.
Keywords: bist methods; built self; test bist; self test ... See more keywords