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Published in 2023 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"
DOI: 10.1109/tcad.2022.3203957
Abstract: Due to the mismatch between the package scaling and the relentless silicon technology scaling, the limited power supply bumps have to bear more stresses on bump reliability. A too high through-bump (TB) current may induce…
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Keywords:
bump current;
methodology;
power;
delivery verification ... See more keywords