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   Articles with "cache memory" as a keyword



Streamlining Active Set Method in MPC using Cache Memory

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recommendations! Published in 2021 at "IFAC-PapersOnLine"

DOI: 10.1016/j.ifacol.2021.08.543

Abstract: Abstract This paper investigates how various caching strategies can reduce the computational effort of the active set method (ASM) applied to solve constrained model predictive control problems with quadratic objective function and linear constraints. Specifically,… read more here.

Keywords: active set; cache memory; cache; set method ... See more keywords

Low power process tolerant nano cache memory for military applications

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recommendations! Published in 2024 at "Australian Journal of Electrical and Electronics Engineering"

DOI: 10.1080/1448837x.2024.2414610

Abstract: ABSTRACT Rapid growth in high-performance battery-powered computing applications, Internet of Things (IoT) and artificial intelligence (AI), has raised the need for low-power integrated circuits. Particularly in military applications, wireless sensor nodes are used to detect… read more here.

Keywords: memory; cache memory; military applications; low power ... See more keywords

Optimizing the Performance of Data Warehouse by Query Cache Mechanism

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recommendations! Published in 2022 at "IEEE Access"

DOI: 10.1109/access.2022.3148131

Abstract: Fast access of data from Data Warehouse (DW) is a need for today’s Business Intelligence (BI). In the era of Big Data, the cache is regarded as one of the most effective techniques to improve… read more here.

Keywords: data warehouse; mechanism; cache memory; cache ... See more keywords

CacheEM: For Reliability Analysis on Cache Memory Aging Due to Electromigration

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recommendations! Published in 2022 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"

DOI: 10.1109/tcad.2021.3121636

Abstract: Electromigration (EM) is crucial for interconnect reliability. This article introduces the implementation and application of CacheEM which targets SRAM cache memory aging due to EM. CacheEM is based on a comprehensive framework including five parts:… read more here.

Keywords: aging due; memory; electromigration; cache memory ... See more keywords

Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus

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recommendations! Published in 2024 at "IEEE Transactions on Circuits and Systems I: Regular Papers"

DOI: 10.1109/tcsi.2024.3438164

Abstract: SRAM performance is highly dominated by interconnects as technology scales down because of the significant parasitic resistance and capacitance in the interconnect. This paper introduces a framework for the co-design of technology, interconnect, and cache… read more here.

Keywords: performance; cache memory; design; tree ... See more keywords