Modeling of Quantum Confinement and Capacitance in III–V Gate-All-Around 1-D Transistors
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DOI: 10.1109/ted.2017.2766693
Abstract: In this paper, a physics-based compact model for calculating the semiconductor charges and gate capacitance of III–V nanowire (NW) MOS transistors is presented. The model calculates the subband energies and the semiconductor charges by considering… read more here.
Keywords: modeling quantum; confinement; gate; capacitance iii ... See more keywords