A Memory-Efficient Hardware Architecture for Connected Component Labeling in Embedded System
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DOI: 10.1109/tcsvt.2019.2937189
Abstract: In this paper, we introduce a hardware architecture to accelerate connected component labeling (CCL) for embedded systems. The proposed CCL architecture scans the given binary image only once, and during the raster scan, the input… read more here.
Keywords: connected component; memory; hardware architecture; component labeling ... See more keywords