Hierarchical Model Checking of SystemVerilog-Specified Asynchronous Circuits for Deadlock Detection
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DOI: 10.1109/tcad.2024.3509798
Abstract: Specifying channel-based asynchronous circuits in SystemVerilog is a promising alternative design paradigm to combine the advantages of asynchronous circuits and industrial electronic design automation supports. However, communicating through channels can be error-prone, potentially introducing deadlocks… read more here.
Keywords: model checking; checking systemverilog; asynchronous circuits; hierarchical model ... See more keywords