An 8T SRAM With On-Chip Dynamic Reliability Management and Two-Phase Write Operation in 28-nm FDSOI
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DOI: 10.1109/jssc.2019.2905343
Abstract: Bias temperature instability (BTI) degradation poses increasingly critical lifetime reliability design challenges in static random access memory (SRAM), as fabrication technology marches toward a very deep nanometer regime. This paper presents circuit techniques that enable… read more here.
Keywords: reliability management; dynamic reliability; chip dynamic; bti ... See more keywords