Off-Chip Memory Allocation for Neural Processing Units
Sign Up to like & getrecommendations! Published in 2024 at "IEEE Access"
DOI: 10.1109/access.2024.3352900
Abstract: Many modern Systems-on-Chip (SoCs) are equipped with specialized Machine Learning (ML) accelerators that use both on-chip and off-chip memory to execute neural networks. While on-chip memory usually has a hard limit, off-chip memory is often… read more here.
Keywords: memory; chip memory; allocation neural; chip ... See more keywords
Multi-Bank On-Chip Memory Management Techniques for CNN Accelerators
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Transactions on Computers"
DOI: 10.1109/tc.2021.3076987
Abstract: Since off-chip DRAM access affects both performance and power consumption significantly, convolutional neural network (CNN) accelerators commonly aim to maximize data reuse in on-chip memory. By organizing the on-chip memory to multiple banks, we may… read more here.
Keywords: bank chip; multi bank; chip memory; cnn accelerators ... See more keywords
Exploration of Balanced Design in Resource-Constrained Edge Device for Efficient CNNs
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Transactions on Circuits and Systems II: Express Briefs"
DOI: 10.1109/tcsii.2022.3183258
Abstract: Convolutional Neural Networks (CNNs) have been widely used in various image recognition applications due to their high precision and high versatility. In order to improve real-time performance, many efficient CNNs with low computational complexity have… read more here.
Keywords: chip memory; design; exploration balanced; efficient cnns ... See more keywords