Investigation of Various Bumps and Redistribution Lines to Inhibit Protected Silicon Nitride Cracks in High Pattern Density Chip Package
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DOI: 10.1007/s11664-020-08310-8
Abstract: Mechanical stress related to chip packaging failure is the most common reliability issue in semiconductor devices, especially for high pattern density of very-large-scale integration. In this paper, redistribution lines (RDL) corresponding to gold and copper… read more here.
Keywords: redistribution lines; high pattern; chip package; pattern density ... See more keywords
Chip-Package-Board Interactive PUF Utilizing Coupled Chaos Oscillators With Inductor
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DOI: 10.1109/jssc.2018.2852325
Abstract: In this paper, a concept of chip-package-board (CPB) interactive physically unclonable function (PUF) is presented as a physical countermeasure against malicious counterfeiting at not only chip fabrication but also at package/board assembly stages. A fully… read more here.
Keywords: puf; chip package; chaos; package board ... See more keywords
Effect of Different PBO-Based RDL Structures on Chip-Package Interaction Reliability of Wafer Level Package
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DOI: 10.1109/tdmr.2020.3004836
Abstract: In this paper, CPI (chip-package interaction) reliability of WLP (wafer level package) was investigated. PBO (Polybenzoxazole)-based RDL (redistribution layer) structure was the primary focus. Firstly, the stress distribution for PBO structures was studied by simulation.… read more here.
Keywords: different pbo; chip package; reliability; package ... See more keywords