Feasibility of plasmonic circuits for on-chip interconnects
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DOI: 10.1016/j.sse.2019.03.066
Abstract: Abstract Feasibility of fabricating plasmonic circuits by complementary metal–oxidesemiconductor (CMOS) compatible processes is presented, and the circuit performances are numerically and experimentally discussed from the viewpoint of operating speed and energy loss. The transmission speed… read more here.
Keywords: feasibility; plasmonic circuits; feasibility plasmonic; cmos compatible ... See more keywords