High Throughput Implementation of SMS4 on FPGA
Sign Up to like & getrecommendations! Published in 2019 at "IEEE Access"
DOI: 10.1109/access.2019.2923440
Abstract: The SMS4 algorithm is a block cipher algorithm, which has the characteristics of high security and easy implementation. However, the optimization and implementation schemes proposed for FPGA platform currently use multi-channel parallel and pipelined architectures… read more here.
Keywords: implementation; sms4; clock cycles; high throughput ... See more keywords
Padding of Multicycle Broadside and Skewed-Load Tests
Sign Up to like & getrecommendations! Published in 2019 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2019.2924319
Abstract: Multicycle tests achieve test compaction by increasing the number of clock cycles between scan operations and reducing the number of tests. Tests in a compact multicycle test set typically have different numbers of clock cycles… read more here.
Keywords: tex math; test; clock cycles; inline formula ... See more keywords