A 6.15–10.9 Gb/s 0.58 pJ/Bit Reference-Less Half-Rate Clock and Data Recovery With “Phase Reset” Scheme
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Transactions on Circuits and Systems I: Regular Papers"
DOI: 10.1109/tcsi.2021.3119907
Abstract: This paper presents a low power injection-locked oscillator (ILO)-type clock and data recovery (CDR) in 40 nm CMOS. An efficient “phase reset” scheme is proposed to periodically realign the clock phase to the rising edge… read more here.
Keywords: clock data; phase; reset scheme; phase reset ... See more keywords
A 0.32–2.7 Gb/s Reference-Less Continuous-Rate Clock and Data Recovery Circuit With Unrestricted and Fast Frequency Acquisition
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DOI: 10.1109/tcsii.2021.3053581
Abstract: This brief presents a design of fast frequency locking 320 Mb/s to 2.7 Gb/s continuous-rate reference-less clock and data recovery (CDR) circuit. A simultaneous coarse/fine frequency acquisition processes are being done to achieve an unrestricted… read more here.
Keywords: clock data; frequency; rate; fast frequency ... See more keywords
A 12-Gb/s Baud-Rate Clock and Data Recovery With 75% Phase-Detection Probability by Precoding and Integration-Hold-Reset Frontend
Sign Up to like & getrecommendations! Published in 2023 at "IEEE Transactions on Circuits and Systems II: Express Briefs"
DOI: 10.1109/tcsii.2022.3212881
Abstract: This brief describes a 12-Gb/s quarter-rate receiver with a current-integrating baud-rate clock and data recovery (CDR) technique. The proposed CDR receives a pre-encoded non-return-to-zero (NRZ) data stream and integrates with 0.5-UI phase offset to extract… read more here.
Keywords: rate clock; phase; baud rate; rate ... See more keywords