Low power aware pulse triggered flip flops using modified clock gating approaches
Sign Up to like & getrecommendations! Published in 2018 at "World Journal of Engineering"
DOI: 10.1108/wje-09-2017-0309
Abstract: PurposeThe purpose of this paper is to design a low power clock gating technique using Galeor approach by assimilated with replica path pulse triggered flip flop (RP-PTFF).Design/methodology/approachIn the present scenario, the inclination of battery for… read more here.
Keywords: methodology; clock gating; power; low power ... See more keywords
Fully Automated Hardware-Driven Clock-Gating Architecture With Complete Clock Coverage for 4 nm Exynos Mobile SOC
Sign Up to like & getrecommendations! Published in 2023 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2022.3219410
Abstract: Automatic clock gating (ACG) is a clock-gating architecture with near zero waste on dynamic power dissipation on global clock distribution network. ACG models global clock structure as a graph with nodes and arcs representing clock… read more here.
Keywords: global clock; gating architecture; structure; clock gating ... See more keywords
Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs
Sign Up to like & getrecommendations! Published in 2017 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"
DOI: 10.1109/tcad.2016.2597215
Abstract: This paper investigates the reduction of dynamic power for streaming applications yielded by asynchronous dataflow designs by using clock gating techniques. Streaming applications constitute a very broad class of computing algorithms in areas such as… read more here.
Keywords: efficient implementations; energy efficient; clock gating; streaming applications ... See more keywords
Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add
Sign Up to like & getrecommendations! Published in 2018 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2017.2784807
Abstract: The need for power efficiency is driving a rethink of design decisions in processor architectures. While vector processors succeeded in the high-performance market in the past, they need a retailoring for the mobile market that… read more here.
Keywords: vector; gating techniques; clock gating; power ... See more keywords