Clock Jitter Reduction and Flat Frequency Generation in PLL Using Autogenerated Control Feedback
Sign Up to like & getrecommendations! Published in 2017 at "IEEE Transactions on Components, Packaging and Manufacturing Technology"
DOI: 10.1109/tcpmt.2017.2751742
Abstract: In this paper, a method has been proposed by which one can reduce the clock jitter and achieve almost flat frequency clock output from the phase-locked loop (PLL), independent of the power supply voltage fluctuation.… read more here.
Keywords: supply; methodology; clock jitter; power ... See more keywords
Performance Bounds of ADC-Based Receivers Due to Clock Jitter
Sign Up to like & getrecommendations! Published in 2023 at "IEEE Transactions on Circuits and Systems II: Express Briefs"
DOI: 10.1109/tcsii.2023.3257844
Abstract: The maximum tolerable clock jitter for high-speed ADCs is pessimistically predicted by Nyquist-rate input sinusoidal tests. We prove that the jitter can be greatly relaxed in the presence of lossy channels in wireline systems. We… read more here.
Keywords: bounds adc; performance bounds; jitter; adc based ... See more keywords
Fractional Spectrum Analysis for Nonuniform Sampling in the Presence of Clock Jitter and Timing Offset
Sign Up to like & getrecommendations! Published in 2020 at "IEEE Transactions on Signal Processing"
DOI: 10.1109/tsp.2020.3007360
Abstract: This paper focuses on analyzing the fractional spectrum of nonuniform sampling which is affected by clock jitter and timing offset. Both cases of single-channel and recurrent samplings with limited bandwidth in the fractional Fourier domain… read more here.
Keywords: nonuniform sampling; clock jitter; spectrum; fractional spectrum ... See more keywords