Articles with "cmos process" as a keyword



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Structural and nanomechanical properties of porous silicon: Cheap substrate for CMOS process industry

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Published in 2020 at "Surface and Interface Analysis"

DOI: 10.1002/sia.6885

Abstract: The surface topology of porous silicon (PSi) is a relevant parameter that decides the compatibility of such substrate with CMOS process. Using standard resistivity (1–10 Ω·cm) of Si substrate to fabricate PSi‐S is a low… read more here.

Keywords: substrate cmos; substrate; industry; process ... See more keywords
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A high-speed lateral PIN polysilicon photodiode on standard bulk CMOS process

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Published in 2017 at "Solid-state Electronics"

DOI: 10.1016/j.sse.2016.12.005

Abstract: Abstract This paper reports a lateral PIN polysilicon photodiode on standard bulk complementary metal-oxidesemiconductor (CMOS) process for monolithically integrated high-speed optoelectronic integrated circuits (OEIC). A nominal undoped polysilicon as the photodetection area is intentionally created… read more here.

Keywords: process; lateral pin; cmos process; standard bulk ... See more keywords
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A 5.2 Gb/s Receiver for Next-Generation 8K Displays in 180 nm CMOS Process

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Published in 2022 at "IEEE Journal of Solid-State Circuits"

DOI: 10.1109/jssc.2022.3155514

Abstract: This article presents a high-speed receiver for next-generation 8K ultra-high-definition TVs. The receiver supports error-free communication between the timing controller and the display driver integrated circuits (DDIs) across various channels. Because the receiver must be… read more here.

Keywords: cmos process; receiver next; next generation; process ... See more keywords
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A 40-GHz 4-Bit Digitally Controlled VGA With Low Phase Variation Using 65-nm CMOS Process

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Published in 2019 at "IEEE Microwave and Wireless Components Letters"

DOI: 10.1109/lmwc.2019.2942013

Abstract: A 40-GHz variable gain amplifier (VGA) with 4-bit digital gain control and low phase variation is designed and fabricated on the 65-nm CMOS process. The digital gain control mechanism is achieved using the presented digital… read more here.

Keywords: low phase; cmos process; phase variation; gain ... See more keywords
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Anti-PVT-Variation Low-Power Time-to-Digital Converter Design Using 90-nm CMOS Process

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Published in 2020 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"

DOI: 10.1109/tvlsi.2020.3008424

Abstract: One of the most important functional units in digital circuitry for synchronization and measurement is time-to-digital converter (TDC) which always requires higher resolution and accuracy. In this brief, a process, voltage, temperature (PVT)-variation-insensitive TDC featured… read more here.

Keywords: digital converter; cmos process; using cmos; time digital ... See more keywords
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High-performance one-dimensional MOSFET array photodetectors in the 0.8-µm standard CMOS process.

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Published in 2022 at "Optics express"

DOI: 10.1364/oe.475687

Abstract: This paper reports a series of novel photodetectors based on one-dimensional array of metal-oxide-semiconductor field-effect transistors (MOSFETs), which were fabricated using the standard 0.8-µm complementary metal oxide semiconductor (CMOS) process. Normally, the metal fingers of… read more here.

Keywords: cmos process; array; standard cmos; one dimensional ... See more keywords
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Impact of Various Thermistors on the Properties of Resistive Microbolometers Fabricated by CMOS Process

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Published in 2022 at "Micromachines"

DOI: 10.3390/mi13111869

Abstract: Microbolometers based on the CMOS process has the important advantage of being automatically merged with circuits in the fabrication of larger arrays, but they typically suffer from low detectivity due to the difficulty in realizing… read more here.

Keywords: cmos process; impact various; resistive microbolometers; various thermistors ... See more keywords