Modeling the Performance of Mosaic Uncooled Passive IR Sensors in CMOS–SOI Technology
Sign Up to like & getrecommendations! Published in 2018 at "IEEE Transactions on Electron Devices"
DOI: 10.1109/ted.2018.2863207
Abstract: This paper analyzes the performance of mosaic nonimaging passive infrared (PIR) sensors fabricated by the CMOS–SOI–MEMS technology. The elementary sensor, forming a subpixel, is a thermally isolated nanomachined CMOS transistor, dubbed TMOS, operating at subthreshold.… read more here.
Keywords: cmos soi; performance mosaic; technology; performance ... See more keywords
Compact and Slow-Wave Tunable 28 nm CMOS-SOI Twisted Hybrid Couplers for 5G Applications
Sign Up to like & getrecommendations! Published in 2024 at "IEEE Transactions on Microwave Theory and Techniques"
DOI: 10.1109/tmtt.2023.3345274
Abstract: This article presents four twisted hybrid couplers exhibiting low insertion losses for 5G applications. Thanks to an accurate pre-sizing methodology and an electromagnetic model, three different twisted hybrid coupler architectures are presented and compared to… read more here.
Keywords: slow wave; hybrid coupler; cmos soi; twisted hybrid ... See more keywords
DFF Layout Variations in CMOS SOI—Analysis of Hardening by Design Options
Sign Up to like & getrecommendations! Published in 2020 at "IEEE Transactions on Nuclear Science"
DOI: 10.1109/tns.2020.2973569
Abstract: Four D flip-flop (DFF) layouts were created from the same schematic in Sandia National Laboratories’ CMOS7 silicon-on-insulator (SOI) process. Single-event upset (SEU) modeling and testing showed an improved response with the use of shallow (not… read more here.
Keywords: soi analysis; dff layout; variations cmos; layout variations ... See more keywords