Efficient Implementation of Multiple Time Coding Lines-Based TDC in an FPGA Device
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DOI: 10.1109/tim.2020.2984929
Abstract: This article presents two principles that make multiple time coding lines (TCLs)-based time-to-digital converter (TDC) implementation in field-programmable gate array (FPGA) device more efficient. A pseudo-segmented delay line allows for saving many logical resources by… read more here.
Keywords: implementation; time; time coding; multiple time ... See more keywords