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Published in 2021 at "Solid-state Electronics"
DOI: 10.1016/j.sse.2021.107960
Abstract: Abstract Z2-FET, a partially gated diode, was explored for ESD protection due to its sharp switching behavior and is also a promising candidate for 1T-DRAM application. Based on detailed TCAD simulations, we develop a pragmatic…
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Keywords:
compact model;
memory operation;
memory;
model including ... See more keywords
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Published in 2019 at "IEEE Electron Device Letters"
DOI: 10.1109/led.2019.2901754
Abstract: A physics-based compact model for retention behaviors of conductive-bridge random access memory (CBRAM) is developed by modeling: 1) the material-dependent metal atom transport from the conductive filament into the electrolyte; and 2) the conduction percolation…
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Keywords:
compact model;
percolation;
physics;
retention behaviors ... See more keywords
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Published in 2023 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"
DOI: 10.1109/tcad.2022.3172599
Abstract: This brief presents a compact model to capture the major difference between high-voltage (HV) and low-voltage MOSFETs, i.e., the carrier velocity saturation effect in the drift region of HV MOSFETs. We discuss the numerical and…
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Keywords:
high voltage;
voltage;
model;
compact model ... See more keywords
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Published in 2017 at "IEEE Transactions on Electron Devices"
DOI: 10.1109/ted.2016.2643162
Abstract: HfOx-based resistive switching device has been explored as one of the promising candidates for the electronic synapses of neuromorphic computing systems due to its high performance, low cost, and compatibility with CMOS technology. To meet…
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Keywords:
based electronic;
compact model;
neuromorphic computing;
hfox based ... See more keywords
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Published in 2018 at "IEEE Transactions on Electron Devices"
DOI: 10.1109/ted.2018.2801025
Abstract: A core scheme including dc and capacitance models of amorphous indium gallium zinc oxide thin-film transistors is presented based on terms of surface potential. Due to the intrinsic physical fact, carrier degeneracy is taken into…
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Keywords:
igzo tfts;
compact model;
model;
core compact ... See more keywords
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Published in 2019 at "IEEE Transactions on Electron Devices"
DOI: 10.1109/ted.2019.2937159
Abstract: In this brief, we upgrade our initial drain current compact model for triple-gate junctionless transistors (JLTs) to a continuous model satisfying the source/drain (S/D) symmetry. This is achieved by reformulating the key equations of our…
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Keywords:
compact model;
triple gate;
current compact;
drain current ... See more keywords
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Published in 2020 at "IEEE Transactions on Electron Devices"
DOI: 10.1109/ted.2020.2988858
Abstract: Due to the increasing importance and complexity of source/drain parasitic resistance (Rsd) in nanoscale CMOS technology and circuit design, a predictive 3-D structure-aware Rsd compact model is developed and comprehensively validated in respect of 7-nm…
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Keywords:
compact model;
sub sub;
resistance;
model ... See more keywords
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Published in 2019 at "IEEE Transactions on Nuclear Science"
DOI: 10.1109/tns.2019.2897329
Abstract: A single-event-enabled compact model for bulk FinFET technologies has been developed and integrated with a process design kit (PDK) and an industry standard electronic design automation tool flow. The compact model incorporates transistor bias dependence…
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Keywords:
compact model;
model;
single event;
bulk finfet ... See more keywords
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Published in 2018 at "Micromachines"
DOI: 10.3390/mi9110599
Abstract: Thin-film transistors (TFTs) have grown into a huge industry due to their broad applications in display, radio-frequency identification tags (RFID), logical calculation, etc. In order to bridge the gap between the fabrication process and the…
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Keywords:
thin film;
compact models;
compact model;
transistors tfts ... See more keywords