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Published in 2023 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2023.3244804
Abstract: In a design that consists of several logic blocks, each logic block may be tested separately using its own compressed test set and on-chip decompression logic. The decompression logic is typically based on a linear…
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Keywords:
compressed tests;
among logic;
sharing compressed;
logic blocks ... See more keywords