A Reliable and High-Speed 6T Compute-SRAM Design With Dual-Split-VDD Assist and Bitline Leakage Compensation
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DOI: 10.1109/tvlsi.2023.3243027
Abstract: Compute SRAM (CSRAM) can be configured to execute efficient in-memory logic computation and search operations, which is made possible by the multirow activation scheme. Nevertheless, simultaneous multirow activation introduces notorious compute access disturbance in 6T-based… read more here.
Keywords: high speed; csram; reliable high; compute sram ... See more keywords