Automated Bitstream-Level Cost-Reliability Design-Space Exploration for SRAM-Based FPGAs
Sign Up to like & getrecommendations! Published in 2025 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"
DOI: 10.1109/tcad.2025.3573225
Abstract: Triple modular redundancy (TMR) is a common approach to mitigate the effects of Single-Event Upsets (SEUs) in Single-Event Upset (SRAM)-based field-programmable gate arrays (FPGAs), where these faults may cause changes in the configuration of logic… read more here.
Keywords: cost reliability; sram based; cost; approach ... See more keywords