A Fractional-N Digital LC-PLL Using Coupled Frequency Doubler With Frequency-Tracking Loop for Wireline Applications
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DOI: 10.1109/jssc.2021.3122986
Abstract: This article presents a 23.9–29.4 GHz digital LC-phase-locked loop (PLL) architecture with a low phase noise (PN) and power-efficient coupled frequency doubler for 224 Gb/s PAM-4 transmitter clocking. The proposed frequency doubler is designed with… read more here.
Keywords: coupled frequency; frequency doubler; frequency; pll ... See more keywords