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Published in 2022 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2022.3199241
Abstract: To design a low-oversampled high-resolution noise-shaping successive approximation register (NS-SAR) analog-to-digital converters (ADCs), two main bottlenecks need to be addressed. One is to implement high-order optimized NS with simple and low-power hardware that maximally preserves…
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Keywords:
loop;
noise;
crff structure;
fourth order ... See more keywords