A 25-Gb/s 270-mW Time-to-Digital Converter-Based $8{\times}$ Oversampling Input-Delayed Data-Receiver in 45-nm SOI CMOS
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DOI: 10.1109/tcsi.2018.2851294
Abstract: This paper presents a time-to-digital converter-based oversampling input-delayed multi-standard adaptable data-receiver architecture which digitizes transitions/threshold-crossings and inter-transition distances inside a time-varying binary input symbol sequence. The presented circuit works by sampling delayed replicas of a… read more here.
Keywords: time digital; input; time; digital converter ... See more keywords