UDIR: Towards a Unified Compiler Framework for Reconfigurable Dataflow Architectures
Sign Up to like & getrecommendations! Published in 2024 at "IEEE Computer Architecture Letters"
DOI: 10.1109/lca.2023.3342130
Abstract: Specialized hardware accelerators have gained traction as a means to improve energy efficiency over inefficient von Neumann cores. However, as specialized hardware is limited to a few applications, there is increasing interest in programmable, non-von… read more here.
Keywords: specialized hardware; udir towards; dataflow architectures; reconfigurable dataflow ... See more keywords
EDWAC: A Deadlock-Free Scheme for Compiling Whole Programs onto Dynamically Reconfigurable Dataflow Architectures
Sign Up to like & getrecommendations! Published in 2025 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"
DOI: 10.1109/tcad.2025.3572343
Abstract: Coarse-grained reconfigurable arrays (CGRAs) have become prevailing to accelerate regular kernels coupled with a host processor. As the end-to-end applications are increasingly complex, it is necessary to consider mapping whole programs onto a monolithic CGRA,… read more here.
Keywords: programs onto; dataflow architectures; reconfigurable dataflow; edwac deadlock ... See more keywords