Built-In Test for Hidden Delay Faults
Sign Up to like & getrecommendations! Published in 2019 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"
DOI: 10.1109/tcad.2018.2864255
Abstract: Marginal hardware introduces severe reliability threats throughout the life cycle of a system. Although marginalities may not affect the functionality of a circuit immediately after manufacturing, they can degrade into hard failures and must be… read more here.
Keywords: delay faults; test; test hidden; built test ... See more keywords
Path Unselection for Path Delay Fault Test Generation
Sign Up to like & getrecommendations! Published in 2023 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2022.3224361
Abstract: Path selection procedures identify path delay faults whose tests detect small delay defects. Path selection criteria are positive in the sense that they point to paths that should be selected, e.g., the longest paths. However,… read more here.
Keywords: procedure; test generation; delay faults; path ... See more keywords