A Novel Charge Pump with Low Current for Low-Power Delay-Locked Loops
Sign Up to like & getrecommendations! Published in 2017 at "Circuits, Systems, and Signal Processing"
DOI: 10.1007/s00034-016-0481-6
Abstract: In this paper, a new charge pump circuit for reducing charge and discharge currents with low power consumption is proposed. Using 1.8 V supply voltage, this proposed charge pump generates maximum 19.9 $$\upmu $$μA current. This charge… read more here.
Keywords: charge pump; charge; delay locked; low power ... See more keywords
Mathematical Model for Delay Locked Loop Discriminator for 5G Demodulation Reference Signal
Sign Up to like & getrecommendations! Published in 2025 at "IEEE Access"
DOI: 10.1109/access.2025.3561159
Abstract: The vulnerable nature of satellite-based positioning systems under certain conditions such as urban canyons and indoors has given rise to the need for alternative positioning system. Cellular signal based positioning is gaining popularity and development… read more here.
Keywords: based positioning; discriminator; mathematical model; delay locked ... See more keywords
A Low-Power Multichannel Time-to-Digital Converter Using All-Digital Nested Delay-Locked Loops With 50-ps Resolution and High Throughput for LiDAR Sensors
Sign Up to like & getrecommendations! Published in 2020 at "IEEE Transactions on Instrumentation and Measurement"
DOI: 10.1109/tim.2020.2995249
Abstract: This article presents a low-power, all-digital multichannel time-to-digital converter (TDC) for light detection and ranging (LiDAR) sensors. The proposed TDC architecture measures the time interval through a coarse counter, middle, and fine delay line-based interpolation… read more here.
Keywords: locked loops; time; low power; delay ... See more keywords
250 MHz Multiphase Delay Locked Loop for Low Power Applications
Sign Up to like & getrecommendations! Published in 2017 at "International Journal of Electrical and Computer Engineering"
DOI: 10.11591/ijece.v7i6.pp3323-3331
Abstract: Delay locked loop is a critical building block of high speed synchronous circuits. An improved architecture of amixed signaldelay locked loop (DLL) is presented here. In this DLL, delay cell based on single ended differential… read more here.
Keywords: locked loop; power; 250 mhz; delay ... See more keywords